1. Field of the Invention
The present invention relates generally to a semiconductor device manufacturing technology, and particularly to a method for forming shallow trench isolation in a semiconductor device.
2. Description of the Related Art
Manufacturing processes for making highly integrated semiconductor devices involve forming a variety of components, such as a transistor, capacitor, metal wiring, etc., in very restricted regions, and forming highly insulated regions to prevent parasitic current leakage between the components.
Conventionally, a local oxidation of silicon (LOCOS) field oxide, formed by oxidizing a silicon substrate, has been widely used for isolating the components of the semiconductor device. However, due to the increase of the integration density, a LOCOS field oxide has become disadvantageous to the formation of integrated circuits, because it generally includes a “bird's beak,” which may invade an active device region. Accordingly, a lot of alternative isolation technologies that are more advantageous to the higher integration of devices have been developed. As a typical example of such alternative isolation technologies, shallow trench isolation (STI) having a superior insulating performance and a relatively small formation area has been widely used for isolating transistors in higher integrated metal oxide semiconductor field effect transistor (MOSFET) and bipolar junction transistor devices.
In a typical STI process, a pad oxide and a pad nitride are firstly formed on an entire silicon substrate in successive order to protect an active device area. A photoresist layer is formed and patterned on the pad nitride by a photolithography process. The photoresist pattern defines an opening over an isolation area of the substrate.
After the exposure of the pad nitride by the photoresist pattern, the pad nitride and pad oxide are partially removed by an anisotropic etching process using the photoresist pattern as an etching mask. This etching process is performed to expose the isolation area in which a trench structure may be formed. Next, the photoresist pattern is removed, and the exposed isolation area of the substrate is then etched in a predetermined depth by an anisotropic etching process using the pad nitride as an etching mask. The isolation trench structure, formed by the aforementioned process, is illustrated in FIG. 1 that shows the silicon substrate indicated as 10, the trench indicated as 20, the etched pad oxide indicated as 22, and the etched pad nitride indicated as 24.
After the trench etch, a trench oxide is formed in the trench 20 and the entire substrate 10. The formation of the trench oxide generally involves a high-temperature heat treatment that may produce or result in damage to the silicon substrate. Accordingly, before the formation of the trench oxide, it is preferable to form a liner oxide on each trench sidewall. The liner oxide serves as a buffer for protecting the trench sidewall from any silicon lattice stress that may be caused by the trench oxide.
The trench oxide, e.g., a chemical vapor deposited (CVD) silicon oxide, is formed over the entire substrate 10, filling the trench 20. This trench oxide also covers the active device area, and it should be selectively removed for device processing to continue. This is accomplished by planarizing the substrate, typically via chemical-mechanical polishing (CMP), using the pad silicon nitride layer over the active device area as a stop layer. This process removes the trench oxide from the active device area while retaining it in the isolation trenches. The pad nitride 24 and pad oxide 22 are then removed, resulting in a highly planar substrate with isolated device areas.
FIG. 2 shows the isolation trench structure filled with the trench oxide. Here, reference numerals 10, 20a, and 30 indicate the silicon substrate, the trench oxide, and a gate oxide to be formed in a subsequent process, respectively.
Referring to FIG. 2, the silicon substrate has a sharp profile at the upper corner (A) of the trench, because the trench is formed by the anisotropic etching process. Consequently, when the gate oxide 30 is formed on the active device area to extend from the trench oxide, the silicon dioxide at the upper corner (A) is formed in the thickness T20, which is much smaller than the thickness T30 of the silicon dioxide at the active device area.
This oxide thinning at the upper corner of the trench may result in degradation of the threshold voltage of the transistor. In addition, the sharp profile of the substrate may induce the electric field concentration and silicon lattice stress at the upper corners of the trench. As a result, the performance of the transistor may be deteriorated.